Ramiro Polla b6803bf104 aarch64: increase default alignment for functions and constants ...

Use 16-byte alignment (align=4) instead of 4-byte (align=2) in the function and
const macros. This improves instruction fetch and NEON load performance on
modern AArch64 CPUs.

2025-05-19 13:20:51 +02:00

..

asm.S

aarch64: increase default alignment for functions and constants

2025-05-19 13:20:51 +02:00

cpu_sve.S

aarch64: Print the SVE vector length in libavutil/tests/cpu.c

2024-09-27 00:06:30 +03:00

cpu.c

aarch64: Add CPU feature flags for SVE and SVE2

2024-09-27 00:04:30 +03:00

cpu.h

aarch64: Print the SVE vector length in libavutil/tests/cpu.c

2024-09-27 00:06:30 +03:00

float_dsp_init.c

Merge remote-tracking branch 'qatar/master'

2014-03-19 02:52:08 +01:00

float_dsp_neon.S

aarch64: Consistently use lowercase for vector element specifiers

2023-10-21 23:25:18 +03:00

intreadwrite.h

avutil/aarch64: add AV_COPY128 and AV_ZERO128 macros

2024-08-26 10:26:59 +02:00

Makefile

aarch64: Print the SVE vector length in libavutil/tests/cpu.c

2024-09-27 00:06:30 +03:00

neontest.h

all: Add missing header guards

2016-01-28 19:49:48 -08:00

timer.h

aarch64: Use cntvct_el0 as timer register on Android and macOS

2024-06-17 14:00:34 +03:00

tx_float_init.c

lavu/tx: refactor to explicitly track and convert lookup table order

2022-11-24 15:58:34 +01:00

tx_float_neon.S

avutil/aarch64/tx_float_neon.S: clean up FFT4_X2

2025-02-28 13:42:54 +01:00