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configure: add detection of assembler support for SME
All changes are made during development/testing of SVE/SME for ffmpeg (vvc). Tested on Apple M4
This commit is contained in:
Georgii Zagoruiko
committed by
Martin Storsjö
Martin Storsjö
parent
2251ede69e
commit
cdb14bc74d
2
Makefile
2
Makefile
@@ -111,7 +111,7 @@ SUBDIR_VARS := CLEANFILES FFLIBS HOSTPROGS TESTPROGS TOOLS \
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MIPSFPU-OBJS MIPSDSPR2-OBJS MIPSDSP-OBJS MSA-OBJS \
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MMI-OBJS LSX-OBJS LASX-OBJS RV-OBJS RVV-OBJS RVVB-OBJS \
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OBJS SHLIBOBJS STLIBOBJS HOSTOBJS TESTOBJS SIMD128-OBJS \
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SVE-OBJS SVE2-OBJS
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SVE-OBJS SVE2-OBJS SME-OBJS
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define RESET
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$(1) :=
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8
configure
vendored
8
configure
vendored
@@ -478,6 +478,7 @@ Optimization options (experts only):
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--disable-i8mm disable I8MM optimizations
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--disable-sve disable SVE optimizations
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--disable-sve2 disable SVE2 optimizations
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--disable-sme disable SME optimizations
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--disable-inline-asm disable use of inline assembly
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--disable-x86asm disable use of standalone x86 assembly
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--disable-mipsdsp disable MIPS DSP ASE R1 optimizations
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@@ -2224,6 +2225,7 @@ ARCH_EXT_LIST_ARM="
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setend
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sve
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sve2
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sme
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"
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ARCH_EXT_LIST_MIPS="
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@@ -2491,6 +2493,7 @@ TOOLCHAIN_FEATURES="
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as_archext_i8mm_directive
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as_archext_sve_directive
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as_archext_sve2_directive
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as_archext_sme_directive
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as_dn_directive
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as_fpu_directive
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as_func
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@@ -2823,6 +2826,7 @@ dotprod_deps="aarch64 neon"
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i8mm_deps="aarch64 neon"
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sve_deps="aarch64 neon"
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sve2_deps="aarch64 neon sve"
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sme_deps="aarch64 neon sve sve2"
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map 'eval ${v}_inline_deps=inline_asm' $ARCH_EXT_LIST_ARM
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@@ -6447,11 +6451,12 @@ if enabled aarch64; then
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# internal assembler in clang 3.3 does not support this instruction
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enabled neon && check_insn neon 'ext v0.8B, v0.8B, v1.8B, #1'
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archext_list="dotprod i8mm sve sve2"
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archext_list="dotprod i8mm sve sve2 sme"
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enabled dotprod && check_archext_insn dotprod 'udot v0.4s, v0.16b, v0.16b'
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enabled i8mm && check_archext_insn i8mm 'usdot v0.4s, v0.16b, v0.16b'
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enabled sve && check_archext_insn sve 'whilelt p0.s, x0, x1'
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enabled sve2 && check_archext_insn sve2 'sqrdmulh z0.s, z0.s, z0.s'
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enabled sme && check_archext_insn sme 'smstop'
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# Disable the main feature (e.g. HAVE_NEON) if neither inline nor external
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# assembly support the feature out of the box. Skip this for the features
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@@ -8211,6 +8216,7 @@ if enabled aarch64; then
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echo "I8MM enabled ${i8mm-no}"
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echo "SVE enabled ${sve-no}"
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echo "SVE2 enabled ${sve2-no}"
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echo "SME enabled ${sme-no}"
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fi
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if enabled arm; then
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echo "ARMv5TE enabled ${armv5te-no}"
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@@ -5,6 +5,7 @@ OBJS-$(HAVE_VFP) += $(VFP-OBJS) $(VFP-OBJS-yes)
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OBJS-$(HAVE_NEON) += $(NEON-OBJS) $(NEON-OBJS-yes)
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OBJS-$(HAVE_SVE) += $(SVE-OBJS) $(SVE-OBJS-yes)
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OBJS-$(HAVE_SVE2) += $(SVE2-OBJS) $(SVE2-OBJS-yes)
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OBJS-$(HAVE_SME) += $(SME-OBJS) $(SME-OBJS-yes)
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OBJS-$(HAVE_MIPSFPU) += $(MIPSFPU-OBJS) $(MIPSFPU-OBJS-yes)
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OBJS-$(HAVE_MIPSDSP) += $(MIPSDSP-OBJS) $(MIPSDSP-OBJS-yes)
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@@ -6,3 +6,5 @@ NEON-OBJS += aarch64/float_dsp_neon.o \
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aarch64/tx_float_neon.o \
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SVE-OBJS += aarch64/cpu_sve.o \
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SME-OBJS += aarch64/cpu_sme.o \
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@@ -72,10 +72,19 @@
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#define DISABLE_SVE2
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#endif
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#if HAVE_AS_ARCHEXT_SME_DIRECTIVE
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#define ENABLE_SME .arch_extension sme
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#define DISABLE_SME .arch_extension nosme
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#else
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#define ENABLE_SME
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#define DISABLE_SME
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#endif
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DISABLE_DOTPROD
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DISABLE_I8MM
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DISABLE_SVE
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DISABLE_SVE2
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DISABLE_SME
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/* Support macros for
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@@ -28,6 +28,7 @@
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#define HWCAP_AARCH64_SVE (1 << 22)
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#define HWCAP2_AARCH64_SVE2 (1 << 1)
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#define HWCAP2_AARCH64_I8MM (1 << 13)
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#define HWCAP2_AARCH64_SME (1 << 23)
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static int detect_flags(void)
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{
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@@ -44,6 +45,8 @@ static int detect_flags(void)
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flags |= AV_CPU_FLAG_SVE2;
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if (hwcap2 & HWCAP2_AARCH64_I8MM)
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flags |= AV_CPU_FLAG_I8MM;
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if (hwcap & HWCAP2_AARCH64_SME)
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flags |= AV_CPU_FLAG_SME;
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return flags;
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}
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@@ -67,6 +70,8 @@ static int detect_flags(void)
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flags |= AV_CPU_FLAG_DOTPROD;
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if (have_feature("hw.optional.arm.FEAT_I8MM"))
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flags |= AV_CPU_FLAG_I8MM;
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if (have_feature("hw.optional.arm.FEAT_SME"))
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flags |= AV_CPU_FLAG_SME;
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return flags;
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}
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@@ -133,6 +138,10 @@ static int detect_flags(void)
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#ifdef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE
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if (IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE))
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flags |= AV_CPU_FLAG_SVE2;
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#endif
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#ifdef PF_ARM_SME_INSTRUCTIONS_AVAILABLE
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if (IsProcessorFeaturePresent(PF_ARM_SME_INSTRUCTIONS_AVAILABLE))
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flags |= AV_CPU_FLAG_SME;
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#endif
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return flags;
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}
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@@ -162,6 +171,9 @@ int ff_get_cpu_flags_aarch64(void)
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#ifdef __ARM_FEATURE_SVE2
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flags |= AV_CPU_FLAG_SVE2;
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#endif
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#ifdef __ARM_FEATURE_SME
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flags |= AV_CPU_FLAG_SME;
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#endif
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flags |= detect_flags();
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@@ -29,9 +29,14 @@
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#define have_i8mm(flags) CPUEXT(flags, I8MM)
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#define have_sve(flags) CPUEXT(flags, SVE)
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#define have_sve2(flags) CPUEXT(flags, SVE2)
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#define have_sme(flags) CPUEXT(flags, SME)
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#if HAVE_SVE
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int ff_aarch64_sve_length(void);
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#endif
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#if HAVE_SME
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int ff_aarch64_sme_length(void);
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#endif
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#endif /* AVUTIL_AARCH64_CPU_H */
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31
libavutil/aarch64/cpu_sme.S
Normal file
31
libavutil/aarch64/cpu_sme.S
Normal file
@@ -0,0 +1,31 @@
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/*
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* Copyright (c) 2025 Georgii Zagoruiko
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "asm.S"
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ENABLE_SME
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function ff_aarch64_sme_length, export=1
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smstart
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cntb x0
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smstop
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ret
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endfunc
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@@ -186,6 +186,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
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{ "i8mm", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_I8MM }, .unit = "flags" },
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{ "sve", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SVE }, .unit = "flags" },
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{ "sve2", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SVE2 }, .unit = "flags" },
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{ "sme", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SME }, .unit = "flags" },
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#elif ARCH_MIPS
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{ "mmi", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMI }, .unit = "flags" },
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{ "msa", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MSA }, .unit = "flags" },
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@@ -76,6 +76,7 @@
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#define AV_CPU_FLAG_I8MM (1 << 9)
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#define AV_CPU_FLAG_SVE (1 <<10)
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#define AV_CPU_FLAG_SVE2 (1 <<11)
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#define AV_CPU_FLAG_SME (1 <<12)
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#define AV_CPU_FLAG_SETEND (1 <<16)
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#define AV_CPU_FLAG_MMI (1 << 0)
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@@ -48,6 +48,7 @@ static const struct {
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{ AV_CPU_FLAG_I8MM, "i8mm" },
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{ AV_CPU_FLAG_SVE, "sve" },
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{ AV_CPU_FLAG_SVE2, "sve2" },
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{ AV_CPU_FLAG_SME, "sme" },
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#elif ARCH_ARM
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{ AV_CPU_FLAG_ARMV5TE, "armv5te" },
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{ AV_CPU_FLAG_ARMV6, "armv6" },
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@@ -174,7 +175,12 @@ int main(int argc, char **argv)
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#if ARCH_AARCH64 && HAVE_SVE
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if (cpu_flags_raw & AV_CPU_FLAG_SVE)
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printf("sve_vector_length = %d\n", 8 * ff_aarch64_sve_length());
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#elif ARCH_RISCV && HAVE_RVV
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#endif
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#if ARCH_AARCH64 && HAVE_SME
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if (cpu_flags_raw & AV_CPU_FLAG_SME)
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printf("sme_vector_length = %d\n", 8 * ff_aarch64_sme_length());
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#endif
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#if ARCH_RISCV && HAVE_RVV
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if (cpu_flags_raw & AV_CPU_FLAG_RVV_I32) {
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size_t bytes = ff_get_rv_vlenb();
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@@ -362,6 +362,7 @@ static const struct {
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{ "I8MM", "i8mm", AV_CPU_FLAG_I8MM },
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{ "SVE", "sve", AV_CPU_FLAG_SVE },
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{ "SVE2", "sve2", AV_CPU_FLAG_SVE2 },
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{ "SME", "sme", AV_CPU_FLAG_SME },
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#elif ARCH_ARM
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{ "ARMV5TE", "armv5te", AV_CPU_FLAG_ARMV5TE },
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{ "ARMV6", "armv6", AV_CPU_FLAG_ARMV6 },
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@@ -1039,7 +1040,13 @@ int main(int argc, char *argv[])
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if (have_sve(av_get_cpu_flags()))
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snprintf(arch_info_buf, sizeof(arch_info_buf),
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"SVE %d bits, ", 8 * ff_aarch64_sve_length());
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#elif ARCH_RISCV && HAVE_RVV
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#endif
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#if ARCH_AARCH64 && HAVE_SME
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if (have_sme(av_get_cpu_flags()))
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snprintf(arch_info_buf, sizeof(arch_info_buf),
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"SME %d bits, ", 8 * ff_aarch64_sme_length());
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#endif
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#if ARCH_RISCV && HAVE_RVV
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if (av_get_cpu_flags() & AV_CPU_FLAG_RVV_I32)
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snprintf(arch_info_buf, sizeof (arch_info_buf),
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"%zu-bit vectors, ", 8 * ff_get_rv_vlenb());
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