added modular mixer channel board

This commit is contained in:
Max Egger
2019-11-15 22:23:07 +01:00
parent 47839b342c
commit b34a70d94d
6 changed files with 4285 additions and 0 deletions
@@ -0,0 +1,3 @@
(fp_lib_table
(lib (name synkie_footprints)(type KiCad)(uri "$(SYNKIE_KICAD)/synkie_footprints.pretty")(options "")(descr ""))
)
@@ -0,0 +1,319 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# synkie_symbols_+5V
#
DEF synkie_symbols_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "synkie_symbols_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# synkie_symbols_-5V
#
DEF synkie_symbols_-5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 50 H I C CNN
F1 "synkie_symbols_-5V" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
X -5V 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# synkie_symbols_BAT54S
#
DEF synkie_symbols_BAT54S D 0 40 Y Y 1 F N
F0 "D" 25 -150 50 H V L CNN
F1 "synkie_symbols_BAT54S" -250 125 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23" 75 125 50 H I L CNN
F3 "" -120 0 50 H I C CNN
$FPLIST
SOT*23*
$ENDFPLIST
DRAW
P 2 0 1 0 -150 0 -50 0 N
P 2 0 1 0 -125 -50 -125 -40 N
P 2 0 1 0 -100 -50 -125 -50 N
P 2 0 1 0 -100 -50 -100 50 N
P 2 0 1 0 -100 50 -75 50 N
P 2 0 1 0 -75 0 75 0 N
P 2 0 1 0 -75 50 -75 40 N
P 2 0 1 0 50 0 150 0 N
P 2 0 1 0 125 -50 125 -40 N
P 2 0 1 0 150 -50 125 -50 N
P 2 0 1 0 150 -50 150 50 N
P 2 0 1 0 150 50 175 50 N
P 2 0 1 0 175 50 175 40 N
P 4 0 1 0 -175 50 -175 -50 -100 0 -175 50 N
P 4 0 1 0 75 50 75 -50 150 0 75 50 N
X ~ 1 -300 0 150 R 50 50 1 1 P
X ~ 2 300 0 150 L 50 50 1 1 P
X ~ 3 0 0 0 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# synkie_symbols_CP_Small
#
DEF synkie_symbols_CP_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "synkie_symbols_CP_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -60 -12 60 -27 0 1 0 F
S -60 27 60 12 0 1 0 N
P 2 0 1 0 -50 60 -30 60 N
P 2 0 1 0 -40 50 -40 70 N
X ~ 1 0 100 73 D 50 50 1 1 P
X ~ 2 0 -100 73 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# synkie_symbols_C_Small
#
DEF synkie_symbols_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "synkie_symbols_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# synkie_symbols_Conn_01x01
#
DEF synkie_symbols_Conn_01x01 J 0 40 Y N 1 F N
F0 "J" 0 100 50 H V C CNN
F1 "synkie_symbols_Conn_01x01" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*
$ENDFPLIST
DRAW
S -50 5 0 -5 1 1 6 N
S -50 50 50 -50 1 1 10 f
X Pin_1 1 -200 0 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# synkie_symbols_Conn_01x10
#
DEF synkie_symbols_Conn_01x10 J 0 40 Y N 1 F N
F0 "J" 0 500 50 H V C CNN
F1 "synkie_symbols_Conn_01x10" 0 -600 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 450 50 -550 1 1 10 f
X Pin_1 1 -200 400 150 R 50 50 1 1 P
X Pin_10 10 -200 -500 150 R 50 50 1 1 P
X Pin_2 2 -200 300 150 R 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 -200 100 150 R 50 50 1 1 P
X Pin_5 5 -200 0 150 R 50 50 1 1 P
X Pin_6 6 -200 -100 150 R 50 50 1 1 P
X Pin_7 7 -200 -200 150 R 50 50 1 1 P
X Pin_8 8 -200 -300 150 R 50 50 1 1 P
X Pin_9 9 -200 -400 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# synkie_symbols_Ferrite_Bead
#
DEF synkie_symbols_Ferrite_Bead FB 0 0 N Y 1 F N
F0 "FB" -150 25 50 V V C CNN
F1 "synkie_symbols_Ferrite_Bead" 150 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Inductor_*
L_*
*Ferrite*
$ENDFPLIST
DRAW
P 2 0 1 0 0 -50 0 -48 N
P 2 0 1 0 0 50 0 51 N
P 5 0 1 0 -109 16 -67 89 109 -12 66 -85 -109 16 N
X ~ 1 0 150 100 D 50 50 1 1 P
X ~ 2 0 -150 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# synkie_symbols_GND
#
DEF synkie_symbols_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "synkie_symbols_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# synkie_symbols_LT1228
#
DEF synkie_symbols_LT1228 U 0 20 Y Y 1 F N
F0 "U" -350 350 50 H V C CNN
F1 "synkie_symbols_LT1228" -250 -300 50 H V C CNN
F2 "" 450 300 50 H I C CNN
F3 "" 450 300 50 H I C CNN
DRAW
T 0 -150 -50 25 0 0 0 + Normal 0 C C
T 0 200 0 25 0 0 0 + Normal 0 C C
T 0 -150 50 25 0 0 0 - Normal 0 C C
T 0 200 100 25 0 0 0 - Normal 0 C C
S -400 300 400 -250 0 0 0 N
P 2 0 1 0 350 50 400 0 N
P 3 0 1 0 -400 0 -350 -50 -200 -50 N
P 3 0 1 0 -400 100 -350 50 -200 50 N
P 4 0 1 0 -400 -150 -350 -200 -100 -200 -100 -50 N
P 4 0 1 0 -200 100 -200 -100 0 0 -200 100 N
P 4 0 1 0 150 150 150 -50 350 50 150 150 N
P 5 0 1 0 400 250 350 200 100 200 100 100 150 100 N
P 6 0 1 0 150 0 0 0 50 0 50 200 -350 200 -400 250 N
X Iout 1 -500 250 100 R 50 50 1 1 P
X -In 2 -500 100 100 R 50 50 1 1 I
X +In 3 -500 0 100 R 50 50 1 1 I
X Vss 4 0 -350 100 U 50 50 1 1 W
X Iset 5 -500 -150 100 R 50 50 1 1 I
X Vout 6 500 0 100 L 50 50 1 1 O
X Vcc 7 0 400 100 D 50 50 1 1 W
X Gain 8 500 250 100 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
# synkie_symbols_Opamp_Dual_Generic
#
DEF synkie_symbols_Opamp_Dual_Generic U 0 20 Y Y 3 F N
F0 "U" 0 200 50 H V L CNN
F1 "synkie_symbols_Opamp_Dual_Generic" 0 -200 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SOIC*3.9x4.9mm*P1.27mm*
DIP*W7.62mm*
MSOP*3x3mm*P0.65mm*
SSOP*2.95x2.8mm*P0.65mm*
TSSOP*3x3mm*P0.65mm*
VSSOP*P0.5mm*
TO?99*
$ENDFPLIST
DRAW
P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f
P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f
X ~ 1 300 0 100 L 50 50 1 1 O
X - 2 -300 -100 100 R 50 50 1 1 I
X + 3 -300 100 100 R 50 50 1 1 I
X + 5 -300 100 100 R 50 50 2 1 I
X - 6 -300 -100 100 R 50 50 2 1 I
X ~ 7 300 0 100 L 50 50 2 1 O
X V- 4 -100 -300 150 U 50 50 3 1 W
X V+ 8 -100 300 150 D 50 50 3 1 W
ENDDRAW
ENDDEF
#
# synkie_symbols_PWR_FLAG
#
DEF synkie_symbols_PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 75 50 H I C CNN
F1 "synkie_symbols_PWR_FLAG" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
X pwr 1 0 0 0 U 50 50 0 0 w
ENDDRAW
ENDDEF
#
# synkie_symbols_R
#
DEF synkie_symbols_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "synkie_symbols_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# synkie_symbols_R_POT
#
DEF synkie_symbols_R_POT RV 0 40 Y N 1 F N
F0 "RV" -175 0 50 V V C CNN
F1 "synkie_symbols_R_POT" -100 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Potentiometer*
$ENDFPLIST
DRAW
S 40 100 -40 -100 0 1 10 N
P 2 0 1 0 100 0 60 0 N
P 4 0 1 0 45 0 90 20 90 -20 45 0 F
X 1 1 0 150 50 D 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
X 3 3 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# synkie_symbols_Trans_PNP_Generic
#
DEF synkie_symbols_Trans_PNP_Generic Q 0 0 Y N 1 F N
F0 "Q" 100 50 50 H V C CNN
F1 "synkie_symbols_Trans_PNP_Generic" 400 -50 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 1 1 0 -50 0 -25 0 N
P 2 1 1 20 -25 -75 -25 75 N
P 2 1 1 0 -25 -25 50 -100 N
P 2 1 1 0 50 100 -25 25 N
P 4 1 1 0 25 50 0 75 -25 25 25 50 F
X B B -150 0 100 R 50 50 1 1 I
X C C 50 -200 100 U 50 50 1 1 P
X E E 50 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library
File diff suppressed because it is too large Load Diff
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update=Thu 14 Nov 2019 11:28:18 PM CET
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.6096
TrackWidth2=0.254
TrackWidth3=0.4064
TrackWidth4=0.6096
TrackWidth5=0.8128
TrackWidth6=1.016
ViaDiameter1=1.524
ViaDrill1=0.8
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.6096
TrackWidth=0.6096
ViaDiameter=1.524
ViaDrill=0.8
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Power
Clearance=0.6096
TrackWidth=0.8128
ViaDiameter=1.524
ViaDrill=0.8
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,3 @@
(sym_lib_table
(lib (name synkie_symbols)(type Legacy)(uri "$(SYNKIE_KICAD)/synkie_symbols.lib")(options "")(descr ""))
)